05 September 2012
Cadence tests IP on TSMC’s 28nm processes
Cadence has made a successful test of its DDR4 sdram PHY and memory controller design intellectual property, proving the technology in silicon manufactured on TSMC's 28HPM and 28HP processes.
"We are excited to be the first to offer silicon proven DDR4 memory controller and PHY IP that will enable our customers to exceed performance and power requirements in their next generation SoCs with reduced risk," said Marc Greenberg, director of product marketing with Cadence's SoC realisation group.
The IP family includes a high speed DDR4 PHY that exceeds the data rates specified in the DDR-2400 draft, while offering interoperability with current DDR3 and DDR3L standards. Also proven in the test chip is a low power digital mobile PHY.
Cadence Design Systems Ltd
This material is protected by Findlay Media copyright
One-off usage is permitted but bulk copying is not.
For multiple copies contact the