04 May 2011
Cadence takes next step on EDA360 odyssey
One year after launching its EDA360 strategy, Cadence has taken what it calls the next step, with the launch of the System Development Suite, a package of four tightly coupled platforms addressing hardware/software codesign.
Mikhal Siwinski, pictured, senior director of product management for system realisation, said the goal of the package was to reduce system integration time by up to 50% and to speed time to market for next generation chip designs. "It's another step towards EDA360," he claimed, "but we are still taking baby steps. We have extended verification to the system level, but it's still not enough."
Claiming that conversations with customers had been at a 'different level' since the announcement of EDA360, Siwinski said two things had become clear: shrinking market windows; and the effect of revenue losses from missing the market. Being six months late in a fast moving market could see revenue cut by $50million, he believed. On top of that, software costs at the 22nm node are likely to push the project cost beyond $120m. He gave the example of the booming tablet market. "At CES in January 2011, there were 102 new tablets announced. But only a handful are shipping after four months and only one will be profitable."
This is seen as a failing from the eda point of view. "EDA has focused on hardware implementation," he admitted. "But software development has little automation, so it's a people cost. And hardware and software are not connected. While there are things you can do in system design, the main issue is the disconnect between hardware and software design."
The four elements in the System Development Suite are: the virtual system platform; the rapid prototyping platform; the incisive verification platform; and the verification computing platform.
Siwinski said the technology, which has been developed internally at Cadence, allows users to work in the same environment. "They use the same debug and have the same analysis," he claimed. "The barriers between technologies have been removed."
Features of the package include integrated multicore hardware/software debug, early device platform creation and tight connection to the RTL flow.
Siwinski admitted the hardware/software codesign problem was nothing new. "But previous solutions have been proprietary or point based. Our strategy is to be open, scalable and connected," he concluded.