10 September 2013 Cadence looks to speed verification with new computing platform In a move to further reduce time to market for semiconductor and system manufacturers, Cadence has introduced the Palladium XP II Verification Computing Platform. The launch is said to speed hardware and software verification significantly. Frank Schirrmeister, senior director, System Development Suite with Cadence, said: "XP II brings 50% more performance and doubles verification productivity through the ability to look at signals, debug and get data back in the box quickly." The XP II platform has been extended to handle designs of up to 2.3billion asic gates while supporting 512 simultaneous users. Schirrmeister said the increased support for users was important, particularly with the growing importance of software development. The roll out also features hybrid technology, which combines the Virtual System Platform with the Palladium XP series to deliver up to 60 times faster embedded OS verification and a tenfold boost in hardware/software verification speed. An embedded test bench supports advanced virtualisation of system environments, enabling users to verify peripheral software drivers prior to tape out. "By bringing better debug productivity, more capacity and support for more users," Schirrmeister concluded, "the curve to confidence that the chip is ready for tape out is steeper." Author Graham Pitcher Comment on this article Websites http://www.cadence.com Companies Cadence Design Systems Ltd This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team. What you think about this article: Add your comments Name Email Comments Your comments/feedback may be edited prior to publishing. Not all entries will be published. Please view our Terms and Conditions before leaving a comment.