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Next-generation SoC production design

Cadence has collaborated with TSMC to accelerate 5nm FinFET innovation.

The collaboration in intended to enable customers’ production delivery of next-generation system-on-chip (SoC) designs for mobile, high-performance computing (HPC), 5G and artificial intelligence (AI) applications on TSMC’s 5nm FinFET process technology.

As part of the work, the Cadence digital, signoff and custom/analogue tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. This is intended to offer extreme ultraviolet (EUV) lithography support at key layers and associated new design rules, which should enable mutual customers to reduce iterations and achieve performance, area, and power improvements.

Some of the newest enhancements for the 5nm process include predictive via-pillar-aware synthesis structuring with the Genus Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling in the Innovus Implementation System and Tempus ECO and also statistical EM budgeting analysis support in the Voltus IC Power Integrity Solution. The newly certified Pegasus Verification System supports 5nm rule decks for all TSMC physical verification flows including DRC, LVS and metal fill.

The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

Author
Bethan Grylls

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