comment on this article

Cadence collaborates with Samsung Foundry

Cadence Design Systems' custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 28nm FD-SOI (28FDS) process technology.

This certification ensures that mutual customers of Cadence and Samsung Foundry will have access to a highly automated circuit design, layout, signoff and verification flow that enables efficient custom design at 28FDS.

The Cadence custom and AMS flow has been created for customers developing automotive, IoT and AI applications at 28FDS technology and features capabilities that are well suited for digitally assisted analog designs. The complete custom and AMS flow that is certified by Samsung Foundry includes the Virtuoso Analog Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Space-Based Router, Spectre Accelerated Parallel Simulator (APS), Voltus-Fi Custom Power Integrity Solution, Quantus Extraction Solution and Physical Verification System (PVS).

The flow provides tools for front-end design, custom layout design, post layout parasitic simulation and electromigration and IR drop analysis and integrated signoff, as well as AMS design.

In addition to the custom and AMS flow certification, a process design kit (PDK) techfile is now Mixed-Signal OpenAccess ready, allowing customers to use the highly integrated Virtuoso-Innovus flow immediately.

Mixed-Signal OpenAccess enables full interoperability between the Virtuoso and Innovus platforms operating on a single OpenAccess design database. This enables users to implement mixed-signal designs in a shorter time and to perform static timing analysis and signoff on a path across digital embedded in mixed-signal hierarchy of multiple blocks, says Cadence.

Cadence has also announced broad support for memory technologies across a range of Samsung Foundry's process technologies targeting high-bandwidth applications.

Cadence has taped out DDR5/4 PHY IP on the Samsung 7nm Low Power Plus (7LPP) process, GDDR6 PHY IP on the Samsung 14nm Low Power Plus (14LPP) process and 2.4G High-Bandwidth Memory 2 (HBM2) PHY IP on the Samsung 10nm Low Power Plus (10LPP) process, which has been recharacterised as the 8nm Low Power Plus (8LPP) process.

In addition, Cadence PHY IP for GDDR6 has achieved silicon success on the Samsung 7LPP process.


Author
Bethan Grylls

Comment on this article


This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team.

What you think about this article:


Add your comments

Name
 
Email
 
Comments
 

Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles