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Breaking the barriers

Shrinking sram cells speeds silicon. By Graham Pitcher.

Philips, STMicroelectronics and foundry TSMC have developed a 0.09um cmos process and are now working on 0.065um and smaller cmos processes. According to the collaborators, the 0.09um process should deliver substantial improvements in speed, power reduction, integration and density. A device designed on the 0.09um process could contain more than 400million transistors, enabling system on chip devices with higher performance, greater complexity and more cost effectiveness.

Test devices were made by ST and Philips on their 12in pilot line at Crolles and by TSMC in Taiwan towards the end of last year. These test chips included 1Mbit and 4Mbit of embedded sram. The sram density of 735kbit/mm2 will be increased by the end of this year when the cell size is reduced from 1.36um2 to 1.27um2.

The process, which can accommodate up to 400,000 logic gates/mm2, has two basic classes of transistor: one is optimised for minimum power consumption; the other is designed for higher speed, general purpose uses. The transistors have gate lengths as short as 0.065um and oxide layers as thin as 1.6nm.

The 0.09um development project extends existing alliances among the three companies. ST and Philips have been developing cmos digital and mixed signal processes for 10 years, whilst Philips and TSMC have been collaborating since 1987.

Author
Graham Pitcher

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