07 June 2011 Automated solution enables effective testing of 3d stacked ICs Automated solution enables effective testing of 3d stacked ICs A new generation of super chips could become a reality following imec's collaboration with Cadence to deliver an automated solution for testing 3d stacked ICs. According to the Belgian research institute, the partnership will provide the design for test (dft) and automatic test pattern generation (atpg) technology to make it easier to test 3d ICs with 'through silicon via' (tsv) functionality. The 3d dft architecture is based on the concept of die level test wrappers and will enable the testing of chips with tsvs at all three stages of stacking. Erik Jan Marinissen, principal scientist at imec, believes the solution will allow electronics companies to create a 'new generation' of super chips. "The imec - Cadence partnership inserts dft structures with minimal area overhead, and the atpg method helps drive towards zero manufacturing defects on the tsvs. This unique offering reduces risk and promotes cost effective fabrication of these chips." Author Laura Hopperton Comment on this article Websites http://www.cadence.com/http://www.imec.be Companies Cadence Design Systems (UK)LtdIMEC This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team. What you think about this article: Add your comments Name Email Comments Your comments/feedback may be edited prior to publishing. Not all entries will be published. Please view our Terms and Conditions before leaving a comment.