12 July 2010
Arithmetic processing IP core features smallest circuit size says Murata
An arithmetic processing IP core for mp3 decoders, designed to use less than 10% of the power required for conventional general software processing, has been unveiled by Murata.
Developed in collaboration with Mathmatec, Murata claims the core features the smallest circuit size and lowest power consumption on the market. This is said to have been achieved by using optimised circuits in conjunction with Mathematec's Spinor circuit compression technology.
The IP core is a circuit of 32,000 gates plus 76kbit of RAM and designed to consume 0.35mW (measured for 44.1kHz 128kbps stereo output, with the core implemented in IBM9SFLP process).
According to Murata, typical power consumption for conventional software processing techniques is approximately 4mW.
Its clock rate is said to be less than 20MHz since real time decoding is possible at 6MHz and the core is compliant with relevant mp3 standards (ISO/IEC11172-3, ISO/IEC13818-3).
Author
Chris Shaw
Supporting Information
Websites
http://www.murata.eu
Companies
Murata Electronics (UK) Ltd
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