comment on this article

Altera and TSMC develop heterogeneous 3D ic test vehicle using CoWoS process

Altera and TSMC develop heterogeneous 3D ic test vehicle using CoWoS process

Altera and TSMC have jointly developed the world's first heterogeneous 3D ic test vehicle using the latter's Chip on Wafer on Substrate (CoWoS) integration process.

Heterogeneous 3D ics are one of the innovations enabling the industry's move beyond Moore's Law, by stacking various technologies within a single device, including analogue, logic and memory. TSMC says its integrated CoWoS process provides semiconductor companies developing 3D ics an end to end solution.

According to Altera, it is the first semiconductor company to develop and complete characterisation of a heterogeneous test vehicle using TSMC's CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ics to ensure they meet yield and performance targets.

Altera says its vision for heterogeneous 3D ics includes developing device derivatives that allow customers to mix and match silicon IP based on their application requirements. The company's 3D ics are designed to enable customers to differentiate their applications by leveraging the flexibility of the fpga, while maximising system performance, minimising system power and reducing form factor and system cost.

"Our partnerships with standards bodies like imec and Sematech, and our use of TSMC's leading edge CoWoS manufacturing and assembly process put us in an excellent position to execute on our strategy of delivering heterogeneous 3D devices to our customers at the right time and with the right set of features," said Bill Hata, senior vice president of worldwide operations and engineering at Altera, pictured. "Implementing heterogeneous 3D capabilities into our devices enables us to continue our path of technology innovation and leadership, and carry us beyond Moore's Law."

CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW On Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing induced warping is avoided. TSMC plans to offer CoWoS as a turnkey manufacturing service.

Chris Shaw

Comment on this article

This material is protected by Findlay Media copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team.

Enjoy this story? People who read this article also read...

What you think about this article:

Add your comments


Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles

Combined testing

Electromagnetic compatibility (EMC) and environmental tests are often treated ...

Change based testing

A major cause of software bugs is inefficient and incomplete testing. This ...

What is EMC testing?

Testing of products under EU guidelines to ensure they don't either pollute the ...

NI Trend Watch 2014

This report from National Instruments summarises the latest trends in the ...

Who can we trust?

It would seem that in the aftermath of the VW emissions scandal, a Pandora’s ...

Roland Steffen, R&S

Graham Pitcher finds out from Roland Steffen how Rohde & Schwarz plans to build ...