According to the partners, a PLL is not only one of the major power consumers in a radio, but can also take up to 30% of the radio area. In contrast, the ADPLL occupies just 0.18mm2 in a 40nm CMOS process and consumes 0.67mW while performing better than digital PLLs.
PLLs have traditionally been analogue components, although researchers have been developing digital alternatives. ADPLLs, the partners assert, enable a smaller footprint, better control and testability and improved scaling to advanced CMOS nodes, but their performance has lagged that of analogue solutions.
Supporting all Bluetooth Low Energy specifications while reducing cost and power consumption to less than any comparable solution, the dividerless fractional-N digital PLL is said to feature power-efficient spur-mitigation and digital phase unwrap techniques.
Kathleen Philips, imec/Holst programme director, noted: “The ADPLL is ready for industrial mass production and is currently being transferred to our industrial partners for product integration.”