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Driving more accurate dynamic power estimation

The activity Plot identifies focus areas over long runs

Integration of emulator with power analysis tools expands analysis and exploration of system-level power consumption.

There are intrinsic limitations in the current approach for estimating dynamic power consumption. Briefly, the approach consists of a file-based flow made up of two steps. First, a simulator or emulator tracks the switching activity either cumulatively for the entire run in a switching activity interchange format (SAIF) file or on a cycle-by-cycle basis for each signal in a signal database file, such as FSDB or VCD. Then, a power estimation tool fed by an SAIF file calculates the average power consumption of the whole circuit, or an FSDB file computes the peak power in time and space for the design.

The method may be acceptable when the design-under-test is relatively small, but when applied to modern, large SoC designs of tens of hundreds or millions of gates executing embedded software, three problems defeat the conventional approach:

  1. The sizes of SAIF and FSDB/VCD files become massive and unmanageable
  2. The file generation process extends to hours, possibly exceeding a day
  3. File loading into a power estimation tool extends to several days or more than a week

New software for the Veloce emulation platform, the Veloce Power Application, eliminates the core problems affecting this approach by eliminating the two-step, file-based flow through a tight integration of the emulator to a power analysis tool.

Instead an Activity Plot maps, in one simple chart, the global design switching activity over time, including while the systems is booting the OS and running live applications.

It identifies time frames of high switching activity that may pose threats to the design. While this chart is not unique, its creation is an order of magnitude faster than the generation-of file-based power charts.

Once high-switching activity time frames are identified at the top level of the design, the design team can zoom into those frames. They can dig deep into the hierarchy of the design and embedded software to uncover the main source of the high-switching activity.

The Dynamic Read Waveform API replaces the cumbersome SAIF/FSDB/VCD file generation process by live-streaming switching data from the emulator into the power analysis tool. All operations run concurrently: emulating the SoC, capturing switching data, reading switching data provided by the power analysis tool, and generating power numbers. The net effect is a jump in overall performance.

With the Veloce Power Application, power analysis and exploration at the system level can be achieved to an extent that is not possible with a file-based flow.

Mentor Graphics

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