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OUTLOOK 2017: Next generation stacked cell structures and new standards are taking flash memory into the future

Peter Lieberwirth, Vice President, Toshiba Electronics Europe

With the explosive growth in mobile devices and society’s reliance on data processing and storage, it is no surprise that the demand for memory is skyrocketing. Nor is it a surprise that such a dynamic market is changing rapidly. Next generation stacked cell structures and new standards are taking flash memory into the future.

At the turn of the Century, optical storage (primarily CD and DVD) was the dominant media. However, today hard disk drives (HDDs) represent two-thirds of all storage media in terms of installed bytes, according to research firm IDC.

IDC also estimates the total storage within the digital universe to be 16Zbyte (Zettabytes: 1021byte) – or 16billion Tbyte of data. While HDDs represent the largest portion, flash memory is clearly the fastest growing sector of this market. Flash, which currently represents around 10% of installed memory, is on a rapidly growing trajectory as technology innovation drives both capacity and reliability and the use of flash-based solid-state storage devices (SSD) becomes more prevalent.

Entering the third dimension
Since its inception, NAND memory has become the non-volatile memory of choice. As a result significant effort (and investment) has been directed to continually squeezing the geometries of the base silicon. In the first 20 years of NAND production, lithographic scaling created ever denser memory chips, leading to process node sizes dropping from 350nm to 15nm. During this time, leading manufacturers moved production to larger wafers and found other ways to drive more automation and efficiencies into their processes.

While die shrinking continued to drive capacities to even higher levels, there were consequences. Cell durability declined as geometries shrunk and the controllers – specifically the error correction code (ECC) engines – became ever more complex. Indeed, controllers were often on the critical path in bringing new technologies to market.

As memory became ever ‘thinner and flatter’, the innovation focus changed. No longer was the primary drive about shrinking geometries ever closer to the bounds of physics. Instead, innovation increasingly focused on devising ways to occupy the volume and not just the area - especially for devices with a capacity of more than 128Gbit.

Enter 3D NAND
A new 48 layer 3D structure termed BiCS – Bit Column Stacked – was developed, with early prototypes being shown in June 2007. This was a quantum leap forward in terms of memory density, replacing the doped polycrystalline silicon of planar NAND with a new silicon nitride layer of charge trap cells. The immediate benefit was to allow far greater capacities in the same footprint.

However, the move was accompanied by substantial performance and reliability benefits. BiCS allows for larger lithographic processes to be used – reversing the trend for die shrinking and increasing cell spacing while reducing cell-to-cell noise and interference. Consequently, write/erase reliability and endurance can be increased dramatically, as can write speeds. Where a typical 15nm 2D NAND device would have sequential write speeds of 20 to 30Mbyte/s, a 3D BiCS process can achieve up to 40Mbyte/s. This equates to a data transfer rate of more than 500Mbit/s.

“3D NAND flash has evolved rapidly and the latest iteration of the technology comes in the form of a 64 layer device that incorporates TLC technology and which offers a capacity of 256Gbit.”

Peter Lieberwirth

Toshiba’s first commercial BiCS based flash memory device was a 48 layer 128Gbit (16Gbyte) 3D NAND chip announced in March 2015. Later that year, Toshiba unveiled the first 256Gbit (32Gbyte) 48 layer BiCS flash device, employing an industry leading 3bit/cell triple level cell (TLC) technology. Thanks to these innovations, it had become possible for BiCS TLC to rival the reliability that had come to be expected from eMMC/MLC NAND flash solutions.

Since then, 3D NAND flash has evolved rapidly and the latest iteration of the technology comes in the form of a 64 layer device that incorporates TLC technology and which offers a capacity of 256Gbit (32Gbyte). This significant advance underscores the potential of this proprietary architecture.

The new 64 layer technology, which is already sampling and will go into mass production in 2017, succeeds the 48 layer BiCS flash, with its leading edge stacking process producing 40% greater capacity per unit chip size than its predecessor. This capacity increase not only reduces the cost per bit, but also increases the manufacturability of memory capacity per silicon wafer. As a result, 64 layer BiCS NAND flash memory can meet the demanding performance specifications of applications ranging from enterprise and consumer solid state disks to smartphones, tablets and memory cards.

Manufacturing support
In order to implement the new processes – and to cope with the anticipated demand for the ultra dense 3D NAND devices, Toshiba continues to make significant investment in facilities and infrastructure.

At Yokkaichi, in the Mie prefecture of Japan, the company operates the world’s largest single complex dedicated to manufacturing NAND flash memory. Here, the company’s capabilities cover more than 50 ‘flavours’ of flash, with the latest facility – known as ‘Fab 2’ – focusing on the manufacture of 3D BiCS flash memory.

Technology supported by standards
As technology develops, new applications emerge. In order to ensure interoperability, standards are defined, upgraded and, in some cases, superseded. That’s why getting the best out of the new NAND flash memory technology and optimising NAND technologies for a given application will also require selection of the most appropriate interface standards.

With flash memory there are two primary standards that are available to take advantage of the new power of NAND flash:

e●MMC (Embedded MultiMediaCard) was designed to cover a wide range of applications in consumer electronics, including smartphones, tablets, servers, printers and navigation systems, as well as some industrial and automotive applications.

Systems defined by e●MMC contain the flash memory itself, along with a flash memory controller thus freeing the host processor from the task of low-level memory management. The result is simplified interfaces, faster development times and processor capacity that can be used for application oriented tasks.

e●MMC is a viable, low cost solution for mobile and other small-footprint applications and has recently seen uptake beyond the consumer world in automotive and industrial applications. However, to take real advantage of the power that 3D NAND can bring to high-performance, high-density mobile, automotive and industrial applications requires a migration to another standard – UFS.

UFS (Universal Flash Storage) is based on the SCSI architecture model and is heavily focussed on embedded and removable flash storage in smartphones and tablets. A key feature of UFS is efficiency: power levels are low when active and drop to near zero when idle. When combined with the specifications for mobile interfaces developed by the MIPI Alliance, this delivers a very low-power architecture that is ideal for today’s power-sensitive mobile devices. With its roots in SCSI technology, UFS (unlike other systems) supports multiple commands, command queuing and multi-thread programming.

The key difference between eMMC and UFS is performance. eMMC supports half-duplexing, meaning the host can read and write, but not at the same time. UFS, on the other hand, supports full duplex operation where the host can read and write simultaneously. This means that UFS is positioned to take full advantage of the capabilities of 3D NAND. The latest version of the standard – UFS 2.0 – doubles the bandwidth to 600Mbit/s and this, combined with multi lane support, facilitates data transfer rates of 1.2Gbit/s.

What’s next?
Looking to the future, 3D NAND seems to be a technology with few limitations. Embedded flash memories with capacities approaching 1Tbit are on the horizon and ruggedised versions suitable for deployment in automotive applications are being planned.

The next milestone on the development roadmap is a 512Gbit, 64-layer device and, with BiCS flash now a tried, tested and proven technology, the ambition is to head to 100 layers and beyond.


Toshiba Electronics Europe
Toshiba Electronics Europe (TEE), the European electronic components business of Toshiba Corporation, offers one of the industry’s broadest IC and discrete product lines, including high-end memory, microcontrollers, ASICs and ASSPs for automotive, multimedia, industrial, telecoms and networking applications. The company also has a wide range of power semiconductor solutions, as well as storage products including HDDs, SSDs, SD Cards and USB sticks.

Formed in 1973, TEE has its headquarters in Düsseldorf and employs approximately 300 people in Europe.

Author
Peter Lieberwirth

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