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Outlook 2016: Avoiding the memory capacity crunch

Peter Lieberwirth, vice president, Toshiba Electronics Europe

Consumer demand for increased memory capacity and performance is driving lithographic innovation in new directions.

The cries for increased memory capacities at lower price points have reached an almost deafening crescendo. Over the next few years, market research firm IDC predicts worldwide installed raw storage capacity will climb from 2,596exabytes (Ebyte) in 2012 to 7,235EB (7.235zettabytes) in 2017. To put this number in perspective, 1Ebyte is 10^18 bytes, or more helpfully, equivalent to the storage available on 31million 32Gbyte iPads.

Until recently, lithographic down-scaling was the most common way to increase memory density – the number of bits that could be stored per unit of silicon. However, recent advances in semiconductor production technologies have enabled engineers to fabricate chips containing three dimensional stacked cell structures. These structures not only answer the clamour for increased bit density, but they also overcome many of the challenges caused by lithographic die shrinks.

With 3D NAND structures now in production, solid-state drives (SSDs) with more than 15Tbyte of storage are just around the corner.

Driving Moore’s law

Since its introduction in 1984, NAND flash technology has been at the forefront of lithographic scaling within the electronics industry. As a consequence, NAND devices are among the densest ICs being produced in volume. Over the past 20 years, the size of the process node has dropped from 350nm to 15nm.

Coupled with the introduction of new cell level technologies that squeeze more bits into each cell, the bit density of planar NAND chips has increased more than 2000 times. Accompanying this increase in density has been a dramatic reduction in the price per Gbyte, a value which has decreased even faster than bit density has increased.

In addition to the cost benefits driven by lithographic scaling, the introduction of more efficient and more automated processes, as well as a shift to larger wafers, have all helped NAND become the storage medium of choice for a wide range of applications.

One of the key challenges for those wanting to use the very latest raw NAND designs in their devices is that new NAND technologies tend to require more powerful error correction code (ECC) engines to be built into the controllers. Another key challenge is that as the lithography shrinks and the bits per cell increase, the durability of the cells decreases.

The development of NAND host controllers has therefore become a critical part of the memory landscape and, generally speaking, there is often a wait for the controllers to catch up with the die shrinks.

Overcoming the limits of lithography

In order to overcome the challenges of die shrinks, whilst increasing bit density, semiconductor manufacturers have developed ways to stack cells on top of each other to form 3D NAND structures.

The basic idea of 3D NAND is to stack the flash storage cells vertically on the silicon substrate. This increases the bit density dramatically compared with planar NAND flash, where the cells are stacked side by side on the chip.

Toshiba has developed a 48-layer 3D cell structure flash memory called BiCS (Bit Column Stacked) that surpasses the capacity of mainstream 2D NAND flash while enhancing write/erase reliability and endurance and boosting write speeds.

The increase in write/erase reliability is achieved because the BiCS technology enables larger lithographic processes to be used while still increasing bit density. In fact, the increase in write/erase reliability and endurance is so dramatic that not only are multi level cell (MLC: 2bit/cell) and triple level cell (TLC: 3bit/cell) devices moving into mass production, but 4bit/cell devices are also being considered.

In the near future, we foresee that both 2D NAND and 3D NAND will co-exist – 2D NAND chips tends to reach a maximum capacity at 128Gbit, while 3D NAND will focus on chips with capacities greater than 128Gbit.

Different structures

A significant change in the structure of the devices is that BiCS architectures use charge trap cells that store electrons in a silicon nitride layer, rather than the doped polycrystalline silicon typical of the floating gate cells used in 2D NAND structures. These new charge trap memory cells are far more durable than the floating gate cells that have been traditionally used and this will reduce cell and drive failures.

In order to progress speeds further, new technologies need to be used to connect the cells together. In the first ‘standard’ 3D NAND devices, each layer is connected using traditional wirebonding techniques.

In collaboration with the New Energy and Industrial Technology Development Organisation, Toshiba has developed a way to incorporate faster, more energy efficient connectors between dies. We recently announced the development of the first 16-die stacked NAND flash memory using through silicon via (TSV) technology to connect the dies in a BiCS structure.

Rather than wirebonding, TSV technology uses the vertical electrodes and vias to pass through the silicon dies for the connection. This enables high-speed data input and output and reduces power consumption.

TSV technology achieves an I/O data transfer rate of more than 1Gbit/s –higher than any other NAND flash memory with a low voltage supply. This enables the power requirements to be reduced by 50% compared to products using wirebonding.

Of course, the future doesn’t stop with 3D. Resistive random-access memory (ReRAM) and phase change memory (PCM) are starting to appear beyond the 3D NAND horizon.

But perhaps the most disruptive memory will be magneto-resistive random access memory (MRAM). MRAM is another form of non-volatile memory that achieves speeds close to DRAM but, unlike NAND, it has virtually unlimited write/erase endurance.

MRAM has the potential to change the way all electronic systems access data. Today, people use NAND flash like a hard disk drive – they copy information from NAND into DRAM and then execute the code itself from the DRAM – a process known as shadowing.

With MRAM, you don’t have to shadow anymore – the data is already in the memory when you turn a device on. MRAM could potentially combine the density of DRAM with the speed of SRAM and non-volatility of NAND – all while consuming a very low amount of power.

The memory revolution is upon us

We live in exciting times; the future of the solid state memory revolution is upon us. Lithographic scaling has already seen die sizes shrink 2000 fold and 3D memory structures will see them shrink further still. These changes will push solid state memory even further into the spotlight and we will see an ever increasing proportion of data stored on solid state memory devices.

These devices will not only enable faster data access, but also revolutionise device design by enabling greater volumes of data to be stored, accessed and analysed more quickly than ever before.

Toshiba Electronics Europe

Toshiba Electronics Europe (TEE) is the European electronic components business of Toshiba Corporation, which is ranked among the world’s largest semiconductor vendors. TEE offers one of the industry's broadest IC and discrete product lines, including high-end memory, microcontrollers, ASICs and ASSPs for automotive, multimedia, industrial, telecoms and networking applications. The company also has a wide range of power semiconductor solutions, as well as storage products including HDDs, SSDs, SD Cards and USB sticks.

TEE was formed in 1973 in Neuss, Germany, providing design, manufacturing, marketing and sales functions. Its headquarters are in Düsseldorf, with branch offices in France, Italy, Spain, Sweden and the UK. TEE employs approximately 300 people in Europe.


Author
Peter Lieberwirth

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