29 February 2012
Free XJTAG Boundary Scan workshop
Wednesday 29th February 2012, Cambridge, UK
This free, full-day workshop session is designed to provide design, development, test and production engineers with a practical hands-on introduction to boundary scan.
Visitors can find out how boundary scan can be used right across the product lifecycle to improve designs, reduce respins and enhance test coverage, fault diagnosis and production yields on complex BGA-populated circuits. The workshop will outline the following:
•Overview of the IEEE 1149.x standards
•How to communicate with the JTAG chain
•Tools to interact with JTAG devices, such as FPGAs or BGAs
•Introduction to board testing using the JTAG chain
•How to describe a circuit in order to enable JTAG testing
•Fault finding abilities of a JTAG connection test
•How to test non-JTAG elements of a board design using boundary scan
"Design, development and test engineers in many leading companies are using JTAG to see ever more deeply inside their systems without having to rely on expensive test fixtures," said Stuart White, XJTAG's workshop co-ordinator. "This is a great opportunity for engineers to see for themselves the speed, power and versatility of boundary scan. That's why we are once again offering these practical hands-on workshops."
Event organiser/promoter
XJTAG
Supporting Information
Websites
http://www.xjtag.com/workshop.php
This material is protected by Findlay Media copyright
See Terms
and Conditions.
One-off usage is permitted but bulk copying is not.
For multiple copies contact the
sales team.