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TI claims ‘dramatic results’ from hafnium dielectric
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14/06/2007
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Texas Instruments plans to integrate a hafnium based ‘high k’ material in the transistors for its 45nm process. The move will reduce leakage by more than 30 times per unit area as compared with silicon oxide gate dielectrics. The approach will also scale to the 32nm process node.
“TI has been at the forefront of hafnium based research and development for nearly a decade and we’re confident that our high k choice overcomes the technological hurdles faced through continued digital cmos scaling and the transition to smaller process geometries,” said Dr Hans Stork, TI’s chief technology officer.
TI will use a chemical vapour deposition (cvd) process to deposit hafnium silicon oxide (HfSiO), followed by reaction with a downstream nitrogen plasma to form HfSiON. Whilst TI says the benefits of hafnium based dielectrics have been widely recognised for the impact on leakage, implementation has presented several challenges. Issues include electrical compatibility with standard cmos processes, as well as challenges in matching the carrier mobility and threshold voltage stability that SiO2 based gate dielectrics have previously delivered.
The nitridation of the cvd HfSiON film delivers the ability to take the approach to the 32-nm node. HfSiON integration has been shown to offer 90% of the SiO2 universal mobility curve, with effective oxide thicknesses of less than 1nm without sacrificing reliability or adding significant cost to the CMOS process.
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Author
Graham Pitcher
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