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Thanks for the memory!
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12/06/2007
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Toshiba has announced a 3d memory cell structure that enhances density and data capacity without relying on advances in process technology, and with minimal increase in the chip die size.
The structure features pillars of stacked memory elements, which pass vertically through multistacked layers of electrode material and which share peripheral circuits. The innovative design is a potential candidate technology for meeting future demand for higher density NAND flash memory.
Toshiba says its approach is based on innovations in the stacking process. Existing memory stacking technologies simply stack 2d memory arrays on top of one another, increasing density but making the manufacturing process longer and more complex.
By contrast, the company says its approach increases memory cell density, is easier to fabricate and does not increase in chip area too much as peripheral circuits are shared by several silicon pillars.
Toshiba’s etching technology drives a hole down through a stacked substrate. Pillars of silicon lightly doped with impurities are deposited to fill in the holes. The gate electrode wraps around the silicon pillar at even intervals and a preformed nitride film for data retention, set in each joint, functions as a NAND cell (circled on the image).
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Author
Graham Pitcher
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