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Renesas to develop new cpu architecture
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22/05/2007
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Renesas is to develop a new cpu architecture that will, it contends, provide revolutionary enhancements over previous generation microcontrollers in code efficiency, processing performance. The compays says it will launch two cpus based on the new architecture to address 16 and 32bit markets, while maintaining compatibility with existing devices.
The new architecture will have innovative advances over the company’s M16C and H8S 16bit cpus and the R32C and H8SX 32bit cpus currently offered. It will combine the code efficiency of the M16C and R32C with the data processing capabilities of the H8S and H8SX. The architecture will also improve power consumption and low noise characteristics of both families.
According to the company, these capabilities will enable it to offer the best overall performance considering code efficiency, processing performance (MIPS/MHz), power consumption and cost competitiveness. Code size is targetted to be cut by 30% and cpu power dissipation by 50%.
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Author
Graham Pitcher
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