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If the CAP fits …
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18/05/2007
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Today’s system designers face many challenges. Designs are becoming more complex incorporating, for example, 32bit risc microprocessors, 256kbyte of sram, DDR2 memory and so on. That complexity brings greater risk of design iterations and delays during the product development phase that can lead to missing market windows and impacting profitability.
Given these trends, many companies have mandated that designs should be implemented using standard products wherever possible to mitigate risk. Standard products minimise the design risk, since they are available off the shelf. However, there are drawbacks. Standard products do not allow customisation and, as there is no way to build company secrets into a standard product, designers need some means to provide custom features.
FPGAs are one approach; they have low upfront costs, but require RTL logic design, synthesis and verification. Verification can be onerous, with numerous detailed test benches required to validate all test cases. Another option is an asic. Standard cell asics offer highly customised, very low unit cost solutions, but have high upfront development costs – more than $1million for a 90nm design with sophisticated IP content – and development time can be 12 months or more for a complex design.
It is clear that designers want a solution that has low upfront costs and low risk. They want the ability to customise the design and to turn it quickly. Atmel believes it can meet these needs with the CAP product line.
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Author
Tim Kubitschek
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