|
TSMC shrinks to 55nm
|
27/03/2007
|
| |
TSMC has unveiled a 55nm process technology, a linear shrink from its existing 65nm process, including I/O and analogue circuits.
According to the company, the process delivers significant die cost savings from 65nm, while offering the same speed and 10 to 20% lower power consumption. Because the 55nm process is a direct shrink, IP providers can use existing libraries and port their 65nm designs with minimal risk and effort. Initial production begins with a general purpose process this quarter, followed by consumer platforms later in the year.
Meanwhile, 55nm CyberShuttle runs are expected to be offered on a bimonthly basis, beginning in May.
“TSMC's half-node process, including 55nm, is the quickest and simplest way for our customers to be cost competitive in the rapidly changing marketplace," claimed Jason Chen, vice president of corporate development of TSMC. "TSMC continues to combine manufacturing superiority with a comprehensive design ecosystem to support customers of any size, from startups to multinational giants."
|
| |
Author
Graham Pitcher
|
| |
| |
|
| Email this article |
| |
|
|
|
|