|
Bug hunting
|
08/01/2007
|
| |
In a move to improve the asic verification process, Synplicity has developed a new approach which it has named TotalRecall. According to John Gallagher, senior director of outbound marketing, it’s ‘3000mpg for asic verification’.
In Gallagher’s view, asic verification continues to be a real issue and one which is being addressed using brute force. “Every new generation brings new bugs and these are getting harder to find,” he claimed. “This means innovative ways are needed to address the problem.”
TotalRecall is an attempt to take the best of two approaches to verification, increasing coverage along the way. “Simulation is best, but slowest,” Gallagher noted, “whilst fpga prototyping is fastest, but offers the least visibility.” However, he added that Synplicity doesn’t want to take simulation away from the designer; rather, it wants to make it better.
Essentially, TotalRecall involves placing the design – which can be the whole asic or a module – into an fpga, along with a ‘clone’ of the design. As the design is stimulated, the same inputs are applied to the clone and these are captured by the stimulus memory buffer. When a bug is detected, engineers can access the buffer to step backwards and forwards through the process and determine the sequence of events that caused the problem.
Although Synplicity is announcing the technology, a product isn’t likely to appear in the short term.
|
| |
Author
Graham Pitcher
|
| |
| |
|
| Email this article |
| |
|
|
|
|