Altera has announced the Stratix III family of fpgas, which it claims offers the lowest power consumption of any high density, high performance programmable logic device.
The devices, which will be produced on TSMC’s 65nm process, are said to consume 50% less power, whilst offering 25% more performance and twice the density of Stratix II parts.
When fully populated, Stratix III will have three variants: Logic, for general applications; Enhanced, for memory and dsp intensive applications; and GX, for high bandwidth designs. At the same time, Altera is announcing HardCopy III for high volume fpga conversions.
For the moment, Logic and Enhanced variants have been announced. The Logic range has seven members, spanning 19,000 to 135,200 adaptive logic modules (ALM). The Enhanced range has four members, covering 19,000 to 101,760 ALMs.
The company has brought two innovative technologies to bear in Stratix III. Programmable power technology allows each logic array block, dsp block and memory block on the chip to work independently in high speed or low power modes. The Power Play feature in it Quartus II software analyses the design, identifies which blocks are in the critical paths and allocates these to high speed mode. All other logic is set to low power operation. Meanwhile, designers can set the core voltage to either 0.9 or 1.1V, for minimum power or high performance respectively.
Athough Altera has announced Stratix III, samples will not be available until the third quarter of 2007.
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