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Time for a change?
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18/11/2005
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It is broadly assumed that pipeline converters provide the highest sample rates whilst yielding high dynamic range. The architecture reduces the number of comparators needed by deploying multiple low resolution flash conversion stages cascaded together to form the ‘pipe’. Although the resolution of each conversion stage is reduced – saving on comparators – the first stage must be designed with linearity at least as good as the maximum resolution of the converter (12bit linearity for a 12bit a/d converter).
Different pipeline implementations exist, but all work by reducing a multibit conversion into several lower resolution ‘flashes’ processed synchronously. At each stage in the pipe, a reconstruction of the previous stage’s quantised output, generated by a d/a converter, is subtracted from the original input signal. The residual signal is then amplified prior to moving onto the following stage. A sample and hold amplifier (SHA) is need to acquire the input signal and to hold it to better than 0.5LSB for the duration of the conversion. Once all substages have a valid conversion result, a digital correction block constructs the final multibit result.
Whilst pipeline a/d converters are capable of high dynamic performance, beyond 12bit resolution, high gain bandwidth is needed to ensure stage settling times fall within the limits set by the high frequency signals being sampled.
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Author
Mark Holdaway
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