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Driving accuracy upwards
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22/04/2005
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Placing large RC networks directly in front of high resolution delta/sigma a/d converters results in input current sampling errors. This, in turn, leads to significant offset and full scale errors. However, a solution to this problem comes with Easy Drive, a fully passive sampling network that cancels differential input current automatically. Easy Drive does not use on chip buffers, which compromise performance. Instead, it uses an architecture that maintains 0.002% full scale error with input RC networks up to 100kO and 10µF.
How does it work?
Delta/Sigma converters achieve high resolution by combining many low resolution conversions into one high resolution result. Most commercially available ÄÓ converters combine hundreds, or even thousands, of 1bit conversions into a single 16, 20, or 24bit result. In order to achieve high resolution, the input is sampled many times during the conversion cycle.
The problem is the input structure of ÄÓ converters is a switched capacitor network. Capacitors are switched rapidly (up to 10MHz) between the input, reference and ground. Each time these capacitors are switched, a current pulse is generated and a complex pattern of charging/discharging pulses is seen at the a/d converter’s input pin. External RC networks that do not settle completely during each sample period cause large full scale errors.
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Author
Mike Mayes
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