Sometime this year, the talking will have to stop. Somewhere in the industry, a company will ‘process lock’ on an approach to the manufacture of a high K dielectric/metal gate stack. Either that, or the semiconductor industry will have to admit to something of a defeat.
If anyone can make the leap, it’s likely to be one of the leading players – Intel has been very aggressive on its plans to introduce these stacks. Because, despite some initial controversy, the high K/metal recipe is now seen as critical for the 45nm node, which those big suppliers would like to hit by 2008.
The flurry of associated research is also an example of the latest phase in the battle between Moore’s Law and the longer entrenched Laws of Physics. The reality is that, right now, the ‘Stop’ sign is looming.
Firstly, let’s recap the fundamental high K issues, even though the topic is more than a decade old.
The 90nm node has taken the thickness of the SiO2 dielectric layer to 1.2nm. At 45nm, that will be closer to 0.8nm. As thickness approaches SiO2’s molecular level, quantum tunnelling current leakage comes into play. Unacceptable levels of power dissipation and heat generation are the two most significant results.
What chip manufacturers want, therefore, are usable materials with a K (or dielectric constant) greater than the 3.9 of SiO2 (hence ‘high’). Such a material must offer greater capacitance and a sufficient molecular/atomic thickness to prevent – or at least mitigate – tunnelling. Several candidates have emerged, including hafnium oxide, titanium oxide and zirconium oxide.
The problem is that such materials tend not to marry too well with traditional polycrystalline silicon (poly Si) electrodes. The biggest issue is Fermi level pinning. Here, gate depletion defects, that emerge at the meeting point of the dielectric and the transistor, push up the threshold voltage and damage performance.
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