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23/02/2010
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Graphene has attracted a lot of attention in the last year or so as a potential material for electronic devices of the future. But problems remain in making it compatible with cmos processes; and hence with semiconductor manufacturing.
 Researchers at Georgia Tech say they have developed a one step process that enables both n- and p-type doping of large area graphene surfaces.
By applying a commercially available spin on glass (SOG) material to graphene and then exposing it to electron beam radiation, the research team created both doping types by simply varying the exposure time, with higher levels of energy producing p-type areas.
"This is an enabling a step toward making possible cmos graphene transistors," said senior research engineer Raghunath Murali.
In volume manufacturing, electron beam radiation may be replaced by a lithography process, Murali said, with the reflectance or transmission of the mask set controlling whether n-type or p-type areas are created.
"Making everything in a single step would avoid some of the expensive lithography steps," he said. "Grey scale lithography would allow fine control of doping across the entire surface of the wafer."
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Author
Graham Pitcher
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