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09/02/2010
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Cadence has released version 9.1 of its Encounter Digital Implementation (EDI) System. Expanded features in the software are said to answer calls for better productivity when developing complex SoCs on leading edge process nodes.
"Semiconductor leaders and ecosystem partners provide us with early insight into emerging challenges and this collaboration is exactly what allows us to get ahead of the curve," claimed David Desharnais, Cadence's group director of design, implementation and verification product management.
According to the company, EDI System 9.1 removes the challenges to design productivity through innovative design exploration capabilities. By combining automatic floorplan synthesis, data abstraction modelling and concurrent macro and standard cell placement, users can quickly find and implement the optimal physical architecture of a chip.
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Author
Graham Pitcher
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