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16/09/2009
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Moving away from its wireless heartland, ARM has outlined two Cortex-A9 MPCore hard macro implementations for TSMC's 40nm G process.
 The development is said to provide silicon manufacturers with a rapid and low-risk route to high performance, low-power Cortex-A9 processor-based devices. One of the implementations is optimised for speed and will enable devices to operate at frequencies greater than 2GHz.
According to the company, advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption.
Eric Schorn, vp of marketing for ARM's processor division, said: "ARM's parallel development of advanced, optimised physical IP components demonstrates a new level of collaborative differentiation while enabling our partners to expand their penetration into high margin domains traditionally occupied by proprietary architectures."
While the speed optimised hard macro implementation will provide system designers with an ARM processor featuring aggressive low power techniques, there is also a power optimised approach, targeted at thermally constrained applications. This hard macro implementation delivers a peak performance of 4000 DMIPS while consuming less than 250mW per cpu when selected from typical silicon.
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Author
Chris Shaw
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