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11/05/2009
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Synopsys has announced IC Validator, said to provide physical verification and sign off abilities for designs targeted at 45nm processes and below.
 The move has been made in response to increasing design complexity, growing numbers of design rules and more stringent design for manufacturing requirements. "All of this needs a more efficient processing engine," said Saleem Haider, senior director of marketing for physical design and DFM tools.
IC Validator features high performance and scalability, sign off quality checking and seamless integration with IC Compiler.
According to Haider, IC Validator allows physical verification to be undertaken as the design progresses, rather than at the end.
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Author
Chris Shaw
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