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21/04/2009
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The first EDA tool for statistical memory analysis has been successfully transferred to Samsung Electronics.
 IMEC's Memory Variability Aware Modeling (MemoryVAM) is a tool designed to anticipate and correct weak design spots before tape out, as well as estimating yield loss due to factors such as cycle time, access time and power consumption caused by process variations.
According to IMEC, MemoryVAM is the first holistic flow capable of percolating process variations from the process technology up to the SoC level. It is capable of tracking statistical processes, design and environmental correlations linked together and across abstraction levels.
MemoryVAM is said to build on IMEC's method to analyse performance metrics of semiconductor memories under process variations. The method requires three input items – a transistor level netlist description of a segment of the memory describing all circuitry involved from input to output; a set of parameters describing the internal architecture of the memory; and information about the variability of the devices and interconnects used in the underlying technology.
IMEC's vice president, smart systems technology officer, said: "With MemoryVAM IMEC completes a missing stepping stone in industrial and academic state of the art design for manufacturing flows which lacked such modeling capabilities for memories. This is especially interesting for embedded srams, which are considered to be the most sensitive component to process variations of today's SoCs. We are excited that the tool is now being successfully used by the product engineering design teams at Samsung Electronics."
Kyu-Myung Choi, Samsung's vice president of design technology, added: "With the collaboration with IMEC, a new novel statistical analysis tool MemoryVAM has become available in our embedded sram design. We expect that MemoryVAM will be helpful for parametric yield modeling of embedded sram design and for understanding the unknown gap between design and silicon results due to process variability in deep sub micron technology below 45nm."
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Author
Chris Shaw
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