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13/04/2009
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With the attention given by programmable logic companies to potential applications, you could be forgiven for assuming the market was covered by a range of devices. But not so, at least in the opinion of Doug Hunter, corporate vice president of marketing for Lattice Semiconductor.
 "The market is segmented," he suggested, "with devices available for high end and low end applications, but there's nothing in between."
In Hunter's opinion, there's a 'huge chunk' of the market that needs mid range performance fgpas and it's that market which Lattice is targeting with the ECP3 family, which it claims features the lowest power consumption of any serdes equipped fpga.
Manufactured on a 65nm process, the ECP3 range features more memory and double the number of multipliers available in previous Lattice devices.
The family has also been optimised to minimise power consumption and boasts a cascadable dsp running at 500MHz. "This is going to be useful for those applications with wide math functions, such as FIR filters," Hunter noted.
What's driving this move? Hunter said: "It's a cost thing. Take wireless communications – 3, 3.5 and 4G – as an example. It's not developing as quickly as anticipated. This means companies are redesigning 3G systems to take out cost by reducing the bill of materials, power consumption and so on."
Power is a continuing issue within the fpga world, increasingly so as the devices are moved to smaller processes. Nevertheless, Hunter boasts the ECP3 range features static power consumption 65% less than that of a Stratix part and 85% less than that of a Virtex-5. "This brings a clear advantage," Hunter claimed. "We have customers using 12 slot chassis, but power constraints mean they often can only populate eight of those slots. Switching to Lattice parts means they can use all slots, increasing their revenue per channel and providing more functionality for the same power consumption."
Lattice says four power components are important in fpga design: quiescent consumption; inrush programming current; static consumption; and dynamic consumption.
It says that engineers want to know what power consumption is as early as possible, which has driven the need for power calculators. "We're offering accurate power modelling with the ECP3 range," said Hunter. "This allows designers to try typical and worst case conditions, with results accurate to within 10% of silicon."
Connectivity is also an important feature of the ECP3 range. Lattice says serdes interfaces are becoming increasingly popular. "We have included an enhanced serdes," said Hunter, "and have gone for a quasi digital approach. However, this is still appropriate for use in backplane and chip to chip applications."
With support for data rates ranging from 250Mbit/s to 3.2Gbit/s, Lattice says it has chosen to focus on Ethernet based standards and PCI-Express, rather than Sonet. "We can support multiple rate protocols from one quad," Hunter explained.
Lattice says the ECP3 serdes has been designed to exceed the jitter and drive requirements of commonly used protocols. Low power has been an important consideration and the company claims a consumption of 90mW per channel when the link is running at 3.2Gbit/s. It also claims the part can support reliable data transmission and recovery over 40in of FR-4 backplane.
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Author
Graham Pitcher
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