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Optimised design for synchronous buck regulator
April 2009 Email to a friend
 
Fairchild Seminconductor's 6MHz synchronous buck regulator has been introduced for designers of cell phones, datacards and netbooks.

Optimised design for synchronous buck regulatorThe Fan5361's optimised design is said to provide 91% peak efficiency and has a light load efficiency at 82% at 1mA load current. By reducing wasted energy, the synchronous DC/DC step down converter is designed to enable longer battery life and less heat dissipation in portable applications that need to accommodate rich functionality.
The 6MHz 600mA Buck regulator allows the use of 470nH chip inductors and 0402 case size input and output capacitors. Compatibility with these passive components allows users to pick chip inductors and capacitors that consume less board space. The DC/DC converter is packaged in a 0.99 X 1.39mm WL-CSP package with a sleek, low profile of 0.6mm, conserving board space for these space constrained applications.
The product uses a proprietary architecture offering robust transient response while consuming low quiescent current and operates at input voltages ranging from 2.3 to 5.5V. Fixed output voltage options are available ranging from 1.0 to 1.82V.

 
Author
Chris Shaw
 
 
Supporting Information
http://www.fairchildsemi.com/
 
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