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09/02/2009
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Success with leading edge chips depends on lowering the costs of design and manufacturing.
 Traditionally, cost benefits came from migrating to a smaller process node, but scaling to 40nm introduces risks that can be disastrous without careful preparation.
To survive the transition to 40nm, tools and methods must be in place that mitigate risk. Perhaps the most important aspect is to have an efficient design flow that enables early estimation of key factors, such as power consumption and area and which uses best in class eda tools for predictable design closure. Sondrel’s design flow automation and management environment helps make the design process reliable and repeatable.
A design management environment helps engineers understand and control the implementation risks and requirements before beginning physical layout. For example, how many power domains are there and what methodology will be used for isolation level shifters, always on connections and distributed power switches? How many modes and corners will you use for timing closure? How will you manage the process and design variability inherent in 40nm ics?
These answers shed light on the detailed requirements for the design flow and help to find the best solutions for each challenge. Where off the shelf tools are not available, teams must employ people with experience and technical know how. This combination of accumulated knowledge, tools and techniques is encoded as the master design flow. Once articulated, this design flow directs all design efforts, minimising risk and uncertainty.
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Author
Vincent Le Bars
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