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Go with the flow
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07/11/2008
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Power management and power integrity sign off is a serious challenge for ic designers, especially at smaller technology nodes. This means dynamic and static power minimisation must begin at the earliest design stage and continue throughout the RTL to GDSII flow.
It is also critical to have a common format throughout the design to improve productivity and minimise design iterations. A true open format, such as the Unified Power Format (UPF), ensures interoperability between different eda vendors.
Power considerations
* Dynamic power
Dynamic power dissipation occurs as logic gates switch states. During switching, power supplies must charge an internal capacitance associated with a gate’s transistors. The gate also must charge any external, or load, capacitances that comprise parasitic wire capacitances and input capacitances associated with downstream logic gate inputs.
The relationship between dynamic power dissipation (Pd), frequency (F), load capacitance (Cload) and supply voltage (V) is:
Pd = F.Cload.V2
As designers reduce a system’s clock frequency, they reduce switching activity. They also can gate a clock signal and distribute it only to the portions of an ic that need the signal at a given time. By balancing delays, they can minimise local data activity, glitches and hazards.
Designers can use two techniques to reduce capacitance: reduce the size of gate circuits; or apply a power aware placement algorithm to minimise the length of critical conductors.
By decreasing supply voltage, designers reduce power consumption, but they also reduce switching speed. To overcome this, different areas of a die can run at different voltages – key chip functions operate at one voltage, other circuits run at lower voltages.
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Author
Yatin Trivedi
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