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Reducing run times
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13/10/2008
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Timing closure is becoming a growing problem with larger chip designs on advanced process technologies. In a move to solve this problem, Mentor Graphics has launched Olympus-SoC, a place and route (P&R) system that allows timing analysis and optimisation to take place in parallel.
Sudhaka Jilla, director of marketing for Mentor’s P&R group, said: “This hasn’t been attempted before because it’s a complex problem. Nevertheless, designers are already getting an x7 improvement in timing analysis and an x4 improvement in design closure.”
Pointing out that some design groups are now putting more than 1billion transistors on a chip, Jilla added: “The number of ‘corners’ is also increasing.” Earlier process technologies perhaps only had four corners, but the latest 65nm designs may have up to 30 corners, along with a number of modes. All this means run times now take hundreds of hours.
Mentor’s approach takes advantage of multicore processors to distribute the load. Jilla explained: “There’s a lot of parallelism if you know what to look for and ways you can parallelise the problem. Our algorithm scans up and down the chain identifying tasks which are independent of each other.”
Already, NEC has used the tool for a 30m gate design with four modes and four corners, a 200MHz main clock and more than 150 derived clocks. According the company, it found almost a factor of four reduction in design closure time.
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Author
Graham Pitcher
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