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IBM tackles 22nm challenges
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September 2008
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IBM has announced the semiconductor industry’s first computationally based process for production of 22nm semiconductors.
Called Computational Scaling (CS), the process is said to enable the production of complex, powerful and energy efficient semiconductors at 22nm and beyond.
CS uses mathematical techniques to modify the shape of the masks and characteristics of the illuminating source at each layer. It features a new resolution enhancement technique that uses source mask optimisation, as well as other approaches such as predictive process modeling, design rule generation, variance control and mask fabrication.
IBM has partnered with Mentor Graphics on a new resolution enhancement technique to enable cost effective printing of 2d patterns for the 22nm node. Source mask optimisation provides a way to minimise the use of double patterning by employing customised sources with optimised mask shapes.
“Our partnership with IBM will ensure production ready technologies are in place when they are needed for the 22nm node,” said Joe Sawicki, general manager of Mentor’s design to silicon division.
To address the gap in raw optical resolution, IBM has partnered with Toppan to ensure timely availability of masks with the required feature sizes.
“It has been more than three years since Toppan and IBM launched our joint development project for advanced photomask process,” said Toshiro Masuda, head of Toppan’s Semiconductor Solutions Division. “We believe our ongoing engineering collaboration will significantly enhance the success of IBM’s computational scaling solution.”
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Author
Graham Pitcher
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