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16bit core to meet asic market needs
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10/07/2008
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Looking to service what it sees as need for 16bit processors for asics, Cambridge Consultants has launched the XAP5 core. Low energy consumption and efficient use of low cost memory are said to make the core suited to cost sensitive high volume products.
Alistair Morfey, technology director and chief architect of the XAP family, pictured, said: “There is a growing range of applications that need a processor with good performance, but they will not tolerate the energy consumption, size and cost of a 32bit core.
“XAP5’s design benefits from our own experience of the asic requirements for portable wireless, sensing and medical devices. Reducing unit cost and power consumption for sophisticated software applications have been the primary goals.”
XAP5 combines 16bit data words with a 24bit address space, supporting programs up to 16Mbyte. Typical applications are expected to include ZigBee and Bluetooth wireless networks, energy metering and embedded asics that require a robust and capable software environment.
XAP5 is delivered as a soft IP core in Verilog RTL, allowing asic designers to select the appropriate manufacturing process and to customise the memory management unit and the interrupt vector controller.
Capable of 68Dhrystone MIPS at 100MHz on a 0.13µm cmos process, the core’s 18k gates require just 0.1mm² of silicon.
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Author
Graham Pitcher
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