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08/05/2008
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Designing drop in pseudostatic memories. By Jarrod Eliason.
 Pseudostatic memories are designed to replace srams, even though their internal operation is not static. Two commercially available technologies are pseudostatic ram (psram) and ferroelectric ram (fram). Whilst psram targets slow sram applications and competes on a cost/bit basis, fram targets battery backed sram applications and competes on the basis of system cost and logistics. FRAM also targets non volatile data acquisition applications.
Address transition detection (ATD) – a particular feature of asynchronous sram – allows address pins to change constantly at any rate for any amount of time. The memory is then guaranteed to output the correct data within tAA (address access time) of the address pins stabilising.
This flexibility allows designers to relax when it comes to controlling the relative timing of memory interface signals. A typical micro with a direct memory interface shows its chip select output and addresses as being driven from the same clock edge (see figure 1). Whilst the timing from CLK to /CS (tCS) and CLK to A (tADR) are usually specified, the relative timing between /CS and A is not usually discussed, much less guaranteed.
For an sram, this doesn’t matter; the only requirement is that tAA is fast enough. The time allowed by the micro is 2T minus the address or chip select propagation delay (the greater of tADR and tCS) and the micro data setup time (tSU). In most cases, tADR and tCS are the same.
In an effort to control pin count, almost every port on modern micros serves more than one purpose. One side effect of function multiplexing is that each pin can have a different internal delay. Unless each delay is controlled specifically, it is likely that at least one address pin will be slightly slower than chip select.
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Author
Jarrod Eliason
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