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Core competence
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09/04/2008
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Cisco Systems has done much thinking since it began designing its latest network processor (npu) chipset. In 2003, the company didn’t know then that the design would include a 40 processor core ic. Nor did it know the chipset would comprise 800million transistors. What Cisco did know, however, was that it would have to approach the design differently in order to meet future packet processing requirements.
“One common theme of network processors, as done by all equipment providers, was that the code was [written as] custom microcode,” said Nikhil Jayaram, director of hardware development for Cisco’s QuantumFlow processor. “Writing in microcode was necessary as chip performance wasn’t keeping pace [with processing demand].”
NPUs have struggled to keep up with increasingly demanding packet processing requirements from first inspecting packet header fields to deeper, more detailed packet inspection. Since process technology and clock speeds have not matched the growing processing demand, designers have used microcode to squeeze performance from a device. “It [writing microcode] is very specialised and requires a detailed understanding of the hardware,” said Jayaram. It also means adding features is a significant undertaking.
Accordingly, Cisco’s first goal with its npu design was to develop a high performance cpu with a development environment and toolkit akin to those of mainstream general purpose microprocessors.
Five years on, the QuantumFlow processor chipset is at the heart of Cisco’s latest family of IP routers, dubbed the ASR-1000 series, launched in March.
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Author
Roy Rubenstein
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