|
Boosting low power design
|
26/02/2008
|
| |
In a move intended to allow design teams to produce more efficient low power devices, Synopsys has announced Eclypse, a suite of system level, verification, implementation and sign off tools. The move is said by the company to boost productivity and reduce risk.
“Eclypse is the result of an intensive, multi year effort to create the most comprehensive and silicon proven solution for low power chip development,” said George Zafiropoulos, Synopsys’ vp of solutions marketing. “Synopsys has aligned its low power tools, IP, methodologies and services into an easy to use solution so design teams can quickly and confidently adopt the most advanced low power techniques.”
Said to build on more than 10 years of low power design expertise, Eclypse delivers several new low power technologies. Enhanced clock gating and low power clock tree synthesis allow designers to optimise their clock structures, whilst achieving required skew and timing goals. Multithreshold leakage optimisation constrains the ratio of Vt options used, whilst enhanced automation for power switch insertion and optimisation enables power planning exploration and ‘what if?’ analyses.
Whilst techniques such as power gating, multivoltage, and dynamic voltage and frequency scaling can ‘dramatically’ reduce power consumption in deep submicron chips, Synopsys claims these approaches often require ad hoc approaches. Eclypse combines an array of techniques, methodologies, standards and automation to simplify advanced low power design and verification.
Eclypse supports the Unified Power Format (UPF) language and open methodologies, including those described in the ‘Low Power Methodology Manual’, coauthored by Synopsys and ARM.
|
| |
Author
Graham Pitcher
|
| |
| |
|
| Email this article |
| |
|
|
|
|